High integration dram controller

Abstract

A memory controller for a dynamic random access memory (DRAM) is described. The memory controller of the present invention provides access to a memory array which uses DRAM banks. The memory controller is adaptable to various types of DRAM banks, such that the memory array is capable of having independent and different configurations of DRAM banks in the memory. The memory controller includes multiple programmable storage registers, where one register is associated with every bank location in the memory array. Each of the programmable registers is independently programmed to contain access parameters that are necessary to access its associated bank. The memory controller of the present invention also includes circuitry which is configured to provide each of the banks in the memory with its necessary control signals in the proper sequence and timing according to the access parameters in its associated storage register. In this manner, the present invention is capable of accommodating DRAM banks of different types in the memory array.