Address transition detection noise filter in pulse summation circuit for

Abstract

A noise filter to eliminate short, multiple pulses output from an address transition detection ('ATD') circuit caused by address line noise occurring during a read operation of a nonvolatile semiconductor memory. The ATD circuit includes a pulse summation circuit. Each address line sends an input pulse to the pulse summation circuit when the address bit corresponding to the address line changes. The pulse summation circuit adds and extends the input pulses to form output pulses. Pulse extension is performed by a delay chain formed by NAND and NOR gates. Each output pulse begins after a first predetermined time from the leading edge of an input pulse. The delay chain is set on the leading edge of each input pulse. The trailing edge of each input pulse determines when the delay chain will begin to reset. The extended pulse ends after a delay caused by the delay chain unless a subsequent pulse leading edge occurs within a second predetermined time from each trailing edge. In this way, short, multiple input pulses are turned into one long continuous output pulse. This prevents the sending of short pulses into sensing circuits where they would cause the wrong data to be sensed and latched.