Data logging apparatus with memory and pattern testing device

Abstract

A data logging apparatus for a device function tester comprises a first shift circuit (1) supplied with an output signal of the tester and a strobe signal for shifting the output of the tester by n rates under the timing of a basic clock (T.sub.0), a second shift circuit (2) for shifting the timing of the basic clock (T.sub.0) by n rates, a write pulse generating circuit (3) supplied with the output signal of the shift circuit (2), a third shift circuit (4) supplied with a memory address signal for shifting it by n rates under the timing of the basic clock (T.sub.0), a fourth shift circuit (5) for shifting a pattern address signal by n rates under the timing of the basic clock (T.sub.0), a first memory (6) supplied with the output signal of the first shift circuit (1) and the output signal of the third shift circuit (1) for storing the result of the test shifted by n rates in response to a write command signal, and a second memory ( 7) supplied with the output of the fourth shift circuit (5) and the output of the third shift circuit (4) for storing the pattern address shifted by n rates in response to the write command signal. Data logging can be accomplished without being affected by variable time intervals of write enable strobe pulses.