The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 1994

Filed:

Apr. 22, 1992
Applicant:
Inventor:

Paul C Tong, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 31 ; 148D / ; 257378 ; 437 59 ;
Abstract

A process for manufacturing both field effect and bipolar transistors provides, in one embodiment, a polycide film over the gate and field oxides on the surface of the semiconductor substrate is patterned such that a protective structure of gate material is formed on top the base region of the bipolar transistor while the gate of the FET is formed. The channel region of the FET is defined by the gate, which also serves as a mask for etching away the gate oxide from the source and drain regions. The protective structure of gate material in the active region of the bipolar transistor is removed just before implantation to form the base of the bipolar transistor. In a second embodiment a silicon nitride oxidation mask for formation of filed oxide regions over the bipolar transistor and the FET active regions is formed and portions of the nitride oxidation mask is removed only from the FET active regions after field oxide regions are formed. The portion of the nitride oxidation mask is left intact through formation of the gate regions of the FET, formation of the oxide spacers of the FET active regions, and the formation of source and drain regions. The nitride oxidation mask over the bipolar active region is removed prior to the base implant step. With the nitride oxidation mask over the bipolar transistor active region, a VT implant into the FET active region is performed.


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