Device for preventing excess erasing of a nand-type flash memory and

Abstract

A device for achieving optimum erasure of the memory cells of a NAND type flash EEPROM. A memory string comprises a bit line, word lines and cell transistors with the gates respectively connected to the word lines and the channels cascaded between the bit line and ground voltage. A high voltage supplying device is connected between the bit line and the memory string for generating a first high voltage. A bit line selection transistor has the channel connected between the high voltage supplying device and the memory string and the gate connected to a bit line selection signal. In a first erasing operation, an erasing voltage applying device applies a first voltage to the gate of the bit line selection transistor and an erasing voltage to the gates of the cell transistors. In a second erasing operation, it applies a second voltage to the gate of selected transistor of the cell transistors, a third voltage to the gates of one group of the cell transistors between the selected cell transistor and the ground voltage, a second high voltage to the gates of another group of the cell transistors between the bit line and selected cell transistor and the gate of the bit line selection transistor, and the first high voltage to the drain of the selected cell transistor.