The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 1994
Filed:
Jul. 09, 1993
Applicant:
Inventors:
Mark R Hartoog, Los Gatos, CA (US);
Robert D Shur, Los Altos, CA (US);
Assignee:
VLSI Technology, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364578 ; 364488 ; 364490 ;
Abstract
A method estimates the interconnect capacitance of a first net in an integrated circuit. The first step of the method includes the generation of a value which indicates how tightly connected to one another are components connected to the first net. The second step of the method includes the prediction of interconnect capacitance of the first net based on the value generated in the first step and a number representing how many components are connected to the first net.
Quick Actions:
Hartoog, Mark. (1994). Method for predicting capacitance of connection nets on an integrated (U.S. Patent No. 5295088). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5295088
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