Trench isolation with global planarization using flood exposure

Abstract

A pad silicon oxide layer is deposited over the surface of a silicon substrate. A silicon nitride layer is deposited overlying the pad silicon oxide layer. Portions of the silicon nitride and pad silicon oxide layers not covered by a mask pattern are etched through and into the silicon substrate so as to provide a plurality of wide and narrow trenches within the silicon substrate that will form the device isolation regions. Channel-stops are selectively ion implanted through the openings into the substrate underneath the trenches. The silicon nitride and pad oxide layers are removed. A thin silicon oxide layer is grown conformally on all surfaces of the substrate and within the trenches. A thick layer of silicon oxide is deposited over the surface of the substrate completely filling the trenches wherein the thick silicon oxide layer is planarized over the narrow trenches but is not planarized over the wide trenches. The substrate is coated with a thick layer of photoresist and is subjected to a low dose flood exposure wherein the upper portion of the photoresist is exposed but the lower portion of the photoresist over the wide trenches is not exposed. The upper portion of the photoresist layer is developed and removed. The thick silicon oxide layer is anisotropically etched back to the surface of the substrate wherein the lower portion of the photoresist acts as a mask to prevent etching into the portion of the thick silicon oxide filling the wide trenches and completing the device isolation of the circuit.