The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 1994
Filed:
Jul. 19, 1991
Seiichiro Kawamura, Tokyo, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A method of forming a semiconductor-on-insulator device comprises the steps of forming a first alignment mark on a semiconductor substrate at a first reference position, forming a diffusion region in the semiconductor substrate at a position defined with respect to the first alignment mark according to a predetermined relationship, providing an insulator layer on the semiconductor substrate to expose a part of an upper major surface of the semiconductor substrate, providing a semiconductor layer on the insulator layer in contact with the exposed upper major surface of the semiconductor substrate, recrystallizing the semiconductor layer by heating up to a temperature above a melting point of the semiconductor layer and cooling down subsequently below the melting point, starting from a part of the semiconductor layer in contact with the exposed upper major surface of the semiconductor substrate and moving laterally along the semiconductor layer, to form a single crystal semiconductor layer having an upper major surface formed with a depression at a second, different reference position, patterning the single crystal semiconductor layer using the depression on the upper major surface of the semiconductor layer as a second alignment mark to form a semiconductor device in alignment with the device region in the semiconductor substrate, wherein the first alignment mark at the first reference position is formed with an offset from the second reference position for the second alignment mark, the offset being chosen to cancel out an expansion of the single crystal semiconductor layer upon the step of recrystallization.