The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 1994
Filed:
Jun. 21, 1991
Applicant:
Inventors:
Mikio Ikeda, Hyogo, JP;
Norihiko Kotani, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
364578 ; 364488 ;
Abstract
A method of logic simulation includes the steps of reading delay time of a logic element itself calculated in advance, converting output logic value of the logic element to a voltage value, forming a circuit equation based on connection information of an output impedance circuit of the logic element, calculating a voltage value at an arbitrary node of the output impedance circuit by solving the circuit equation, and converting a voltage value of an input node of a logic element of the succeeding stage to a logic value.