Data transmission circuit

Abstract

A data transmission circuit capable of a high-speed data input/output operation and a large-scaled integration for use in a semiconductor memory device, is disclosed. The data transmission circuit has at least one memory cell 51, a word line 52, a pair of bit lines 65, 66, a sense amplifier 55, and a pair of isolation transistors 53, 54. Further, the circuit includes a pair of common input/output lines 67, 68 for transmitting input or output data with a complementary logic operation, a discharging transistor 56 receiving a control signal at its gate and having a channel connected with a ground voltage node, for transferring an electric potential applied to one end of the channel into the ground voltage level, and a pair of transmission transistors 59, 60 receiving the control signal at their respective gates and having each channel connected with the common input/output lines. Two pairs of input transistors 61, 62 and 63, 64 are connected with the bit lines, their channels each being connected between the bit lines 65, 66 and the transmission transistors 59, 60, their gates each connected with the input/output lines. A pair of output transistors 57, 58 each have a gate electrode connected to the bit lines, and having a channel connected between the channel of the discharging transistor 56 and the channel of the transmission transistors 59, 60. To control electrodes of the discharging transistor 56 and the first and second transmission transistor 59, 60 is applied a column selection line (CSL) signal.