The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 1994
Filed:
Nov. 02, 1992
Cyrus S Bamji, Fremont, CA (US);
Ravi Varadarajan, Fremont, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A computer system and computer-implemented method for compacting the geometrical area of a hierarchical integrated circuit layout. The present invention is particularly adapted for use with layouts including over-the-cell routing (OTCR). The inventive method includes the general steps of normalizing the cells, compacting the cells, then reconstructing the layout that includes the normalized cells. More particularly, the step of normalizing the cells includes initial step of identifying an overlapping object produced from the OTCR that overlaps one of the instances. That overlapping object is then divided into an overlapping segment and a non-overlapping segment. The overlapping segment is then removed from the cell and copied into the leaf cell of the overlapped instance. The overlapping segment is defined as a special object of the cell into which it is copied.