The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 1994

Filed:

Jul. 01, 1991
Applicant:
Inventors:

Jerome A Frankeny, Taylor, TX (US);

Richard F Frankeny, Austin, TX (US);

Joseph LaTorre, Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
174263 ; 174260 ; 439483 ; 2281801 ; 2281802 ; 361774 ; 361784 ;
Abstract

A method of fabricating a substrate module is provided that includes cavities of a diameter and depth which take into account the statistical variance in the dimensions of C4 solder balls. By constructing cavities with the proper dimensions, electrical connection between the chip and substrate, via the solder balls, can be ensured. Further, an annular shoulder is provided which acts as a positive stop to prevent any over travel of the C4s within the cavity, thereby allowing a great deal more pressure to be applied to seat the chip than possible with conventional methods. The present invention also provides processes for applying a coating of material onto the substrate which acts as an adhesive and sealant. This material is provided intermediate any of the holes or cavities (vias) which may be contained within the substrate, and is not deposited in these vias such that no interference is encountered when attaching the chip by way of the C4 solder balls thereon. Chips, or additional substrate layers are then placed onto the substrate, thereby forming a sealed integrated circuit module, which has adhesive between the chip and carrier layers.


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