The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 1994
Filed:
Apr. 14, 1992
David B Noddin, Eau Claire, WI (US);
Robin E Gorrell, Eau Claire, WI (US);
William G Petefish, Eau Claire, WI (US);
Kevin L Stumpe, Altoona, WI (US);
Boydd Piper, Eau Claire, WI (US);
Deepak N Swamy, Eau Claire, WI (US);
Jimmy Leong, Eau Claire, WI (US);
Michael R Leaf, Hammond, WI (US);
Supercomputer Systems Limited Partnership, Eau Claire, WI (US);
Abstract
A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer. When the conductive pad layers of two or more subsections are aligned and stacked together, the interconnect pads can be mechanically and electrically joined together using solid state diffusion to join the donor metal layer and the top metal layer to form an area array interconnection without bonding the surrounding dielectric substrate.