The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 1994
Filed:
Mar. 14, 1991
Toru Otsubo, Fujisawa, JP;
Yasuhiro Yamaguchi, Chigasaki, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
Disclosed herein are an insulating film forming method for semiconductor device interconnection and a plasma treatment system for use in the method. The method comprises (i) a step of forming an insulating film free of void, on a substrate having an interconnection pattern, in which a mixed gas of a film forming source gas and an etching gas comprising a fluorine compound is used to perform both deposition of an insulating film by plasma CVD and reactive etching of the insulating film, simultaneously, and (ii) a step of planarizing the surface of the insulating film formed by the step (i) and comprised of, for example, silicon oxide, in which a gas of a material decomposable by a reactive gas capable of decomposing the insulating film is supplied onto the substrate so as to deposit a solid film of the material, e.g. Si(OCH.sub.3).sub.4, on the insulating film on the substrate, the temperature of the substrate is then raised to liquefy the deposited material film, thereby planarizing the surface of the material film, the substrate temperature is again lowered to solidify the planarized liquid material film, and thereafter the insulating film together with the Si(OCH.sub.3).sub. 4 solid film is subjected to plasma etching with, for instance, CF.sub.4 gas as an etching gas. According to the invention, an insulating film which is planar and free of voids can be formed on an interconnection pattern of a substrate, without affecting the characteristics of devices provided on the substrate.