The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 1994
Filed:
May. 28, 1992
Applicant:
Inventors:
Takehisa Yamaguchi, Hyogo, JP;
Masahiro Shimizu, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 41 ; 437 42 ; 437 44 ; 437162 ;
Abstract
An MIS transistor includes insulating layers formed by the CVD method as gate insulating layers. The gate insulating layers by the CVD method are formed having a uniform film thickness on the channel region surface roughed by etching treatment or the like. The dielectric breakdown strength of the gate insulating layer is thus assured.
Quick Actions:
Yamaguchi, Takehisa. (1994). Method of manufacturing mis type fet semiconductor device with gate (U.S. Patent No. 5275960). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5275960
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile