The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 1993

Filed:

Jan. 15, 1993
Applicant:
Inventors:

Jenoe Tihanyi, Munchen, DE;

Ludwig Leipold, Munchen, DE;

Rainald Sander, Munchen, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307572 ; 307568 ; 307574 ; 307548 ; 307546 ; 307270 ; 323274 ; 323279 ; 323284 ;
Abstract

A circuit configuration for limiting current flowing through a power MOSFET includes a voltage divider being connected between drain and source terminals of the power MOSFET and having a node at which a voltage following a drain-to-source voltage of the power MOSFET drops. A control transistor has a load path connected between the gate terminal and the source terminal of the power MOSFET. The control transistor is made conducting as a function of the voltage at the node of the voltage divider if the drain-to-source voltage of the power MOSFET exceeds a predetermined value. A resistor is connected between the gate terminal of the control transistor and the gate terminal of the power MOSFET. A depletion FET has a drain terminal connected to the gate terminal of the control transistor. The source terminal of the depletion FET is connected to the node of the voltage divider. The gate terminal of the depletion FET is connected to the source terminal of the power MOSFET.


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