The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 1993

Filed:

Sep. 10, 1992
Applicant:
Inventors:

Shinichiro Kimura, Kunitachi, JP;

Shoji Shukuri, Koganei, JP;

Hiromasa Noda, Suginami, JP;

Digh Hisamoto, Kokubunji, JP;

Hideyuki Matsuoka, Kodaira, JP;

Kazuyoshi Torii, Kodaira, JP;

Natsuki Yokoyama, Mitaka, JP;

Toshiyuki Yoshimura, Kokubunji, JP;

Kazunori Tsujimoto, Higashiyamato, JP;

Eiji Takeda, Koganei, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 41 ; 437 40 ; 437 44 ; 437162 ;
Abstract

A very thin oxide film is formed at an opening formed in an insulator film and a conductor layer, on a substrate, and impurity-containing polysilicon is formed on the sidewall of the opening. Impurity diffusion from the from the silicon into the substrate through the very thin oxide film causes a lowering in effective concentration of the diffused impurities, resulting in the formation of shallower source/drain region. Thereafter, a gate insulator film and a gate electrode are formed on the substrate surface in an area bounded by an insulator film formed on the sidewall of the opening. The gate electrode smaller than the opening, the size of which corresponds to the limit of processing, and the shallower source/drain region afford a miniaturized MOSFET.


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