Memory efficient topological converter assembly

Abstract

A memory testing assembly (50) for testing a memory device under test ('DUT') includes a row address converter (58) and a column address converter (62). The row and column address converters translate generic row and column count signals into correct row and column address signals that address desired memory cells in a particular DUT. The row and column address converters comprise separate memory arrays, which allow them to employ a relatively small amount of memory bits. The row and column address converters are, however, cross-coupled to provide row and column information signals that are fed back to inputs of the respective column and row address converters. Such feedback allows the memory tester to be able to test DUTs for which some of the row addresses must be known to translate the column addresses and/or some of the column addresses be known to translate the row address. The memory tester writes data into the cells of the DUT and reads and compares the read data with the previously written data. The memory tester includes a data pattern generator (74) that controls the data topology of the data written into cells of the DUT.