Ac miller-killer circuit for l.fwdarw.z transitions

Abstract

A circuit to be used with tristate output buffers as a means of diverting from the output pulldown transistor control nodes Miller Current arising while the output buffer is being switched from the low-active state L to the inactive state Z. The circuit complements a DC Miller Killer circuit, relieving the latter from having to deal with this transient, and hence permitting a down-sizing of the DCMK transistor. The net effect is a significantly faster L.fwdarw.Z transition for the tristate buffer and a slightly faster Z.fwdarw.L transition, all accomplished without degrading the DC Miller Killer protection against L.fwdarw.H bus transitions. The key to the present invention is its use of the time interval between the respective, sequential switching of the enable buffer outputs, E and EB following the application of a disable signal to this enable buffer. The present invention includes circuitry which ensures that its Miller Killer transistor is conducting only during the transient associated with the L.fwdarw.Z switching. One embodiment for accomplishing this is to connect the control node of an 'LZ/ACMK' transistor to the high-potential power rail through two control transistors wired in series. Then, by arranging the circuitry so that both control transistors are conducting only when E and EB are both logic-low, a situation which arises only in the midst of a transition of the output buffer into its Z state, the desired AC operation of the present Miller Killer is achieved.