Advanced phase locked loop circuit

Abstract

A PLL circuit comprises a voltage controlled oscillator responsive to a control signal to output an output signal having a variable oscillation frequency; a phase detector for making a phase comparison between the output signal from the voltage controlled oscillator and a reference signal, and for outputting an output error signal; an integrator for integrating the output error signal from the phase detector to extract a direct current variable component contained in the output error signal, the integrator having a first cutoff frequency; and a loop filter for feeding the direct current variable component from the integrator to the voltage controlled oscillator as the control signal to synchronize the output signal from the voltage controlled oscillator with the reference signal. An alternate current coupling circuit is provided for adding only an alternate current component contained in the output error signal from the phase detector to the control signal for feeding to the voltage controlled oscillator; and a compensating circuit is inserted in an alternate current signal path of the alternate current coupling circuit. The compensating circuit is inserted in an alternate current signal path of the alternate current coupling circuit. The compensating circuit has a second cutoff frequency exceeding the first cutoff frequency of the integrator, so that a wide band characteristic is obtained, and SSB phase noise suppression is improved.