The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 1993

Filed:

Oct. 04, 1991
Applicant:
Inventor:

Ichiro Murai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257306 ; 257335 ; 257412 ; 257607 ;
Abstract

A MOS type semiconductor memory device comprises a silicon (Si) substrate of a first conductivity type and a memory cell on a main surface of the Si substrate including a MOS transistor with a first and a second diffused layer highly doped with opposite second conductivity type impurities which provide a source and a drain region spaced apart in the main surface, a gate electrode of a conductive material formed through an insulating layer between the two highly doped diffused layers; an inter-layer insulating film formed to cover the MOS transistor; a capacitor cell formed on the inter-layer film including a lower electrode layer of conductive material formed on the inter-layer insulating film, a portion of which extends through a contact hole formed in the inter-layer insulating layer to penetrate through this layer to reach the junction adjacent to one of the highly doped diffused layers, a dielectric film on the lower electrode layer, and an upper electrode layer formed on the insulating film; and a double-diffused layer doped with the second conductivity type impurities formed to overlap with one of the two highly doped diffused layers at the junction of the Si substrate to make an electric contact between the source-drain circuit of the MOS transistor and the lower electrode.


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