The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 1993
Filed:
Sep. 03, 1992
Kuang-Chao Chen, Taipei, TW;
Shaw-Tzeng Hsia, Taipei, TW;
Industrial Technology Research Institute, Hsinchu, TW;
Abstract
A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via an integration of siloxane partial etchback and silicate processes. A first intermetal dielectric layer, thinner than that in conventional partial etchback methods, is deposited. This is covered with a siloxane spin-on-glass layer with no voids. This layer is baked, but not cured. The siloxane is partially etched back to the underlying metal layer resulting in a loss of planarity. An undoped silicate spin-in-glass coating is applied and baked followed by the curing of both the siloxane and silicate spin-on-glass layers. This results in excellent planarity with no cracking of the cured spin-on-glass. Most importantly, this method can be used for submicron technologies having conductor lines which are spaced from one another by submicron feature size.