The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 1993
Filed:
Feb. 25, 1991
Applicant:
Inventors:
Milton M Hood, Jr, Lake Oswego, OR (US);
David L Rutledge, Newberg, OR (US);
Kapil Shankar, San Jose, CA (US);
Rudolf Usselmann, Mountain View, CA (US);
Assignee:
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307465 ; 3074651 ; 307471 ;
Abstract
A macrocell is provided for use in logic circuits which is capable of being configured into any one of six different states so as to replicate an X-type output architecture, an L-type output architecture and a number of hybrid architectures which encompass features from one or both of these types.
Hood, Jr, Milton. (1993). Output logic macrocell (U.S. Patent No. 5245226). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5245226
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