The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 1993

Filed:

Aug. 26, 1991
Applicant:
Inventor:

Naoki Yamauchi, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518912 ; 365218 ; 365233 ; 365236 ;
Abstract

Data in an EEPROM contained in a microcomputer integrated circuit device is erased and re-writing. Upon a detection of a start bit of the data, data of a plurality of bits is accepted in a shift register in response to a clock signal applied from a synchronization circuit. A counter counts clock signals up to the number corresponding to the data of a plurality of bits to inhibit data writing in the shift register. The data accepted in the shift register is temporarily stored as bit parallel data of a plurality of bits in a receiving buffer and selected by a selector to be applied to the EEPROM. The data is written, by a write control circuit, at an address in the EEPROM designated by an address counter.


Find Patent Forward Citations

Yamauchi, Naoki. (1993). Data erasing and re-writing circuit for use in microcomputer integrated (U.S. Patent No. 5243561). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5243561

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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