Methods and apparatus for improved quotient correction in nonrestoring

Abstract

A hardware logic arrangement for quotient correction in high speed higher radix non-restoring division computation circuits producing alternative quotient results of the form Q and Q-1. A two bit per clock quotient bit stream is taken as the output from an divider and selectively latched into positive and negative weighted quotients. These redundant vectors are then seperately steered via appropriate steering logic to a carry-propogate-adder (CPA). An exclusive-OR (XOR) logic block is inserted between the steering logic for one of the vectors and the subtrahend input of the CPA. Operation of the XOR block is governed by a first control signal. A second control signal is coupled to the carry-in input of the CPA. After the last iteration of the division sequence, either Q or Q-1 alternative forms of the result quotient may be produced in the clock cycle required by selectively invoking 2's complement addition when combining the redundant weighted quotients. Where the quotient Q is required, asserting the first control signal to the XOR block inverts the datavalue transmitted to the subtrahend input of the CPA, whereafter both addend and subtrahend inputs are added together in the presence of the second control signal asserted to the carry-in input of the CPA, adding 1 to the sum. Where the alternative result Q-1 is required, only the first control signal is asserted to the XOR block to invert the datavalue transmitted to the subtrahend input of the CPA, whereafter the addend and subtrahend inputs are simply added together.