Frasable non-volatile semiconductor memory device having read/write test

Abstract

An erasable non-volatile semiconductor memory device has a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detects the write status of each memory cell by a differential type detection circuit through first and second bit lines connected to the two cell transistors. Further, the erasable non-volatile semiconductor memory device sets all cell transistors constructing a plurality of the memory cells to the erasing status or write status in entirety, and controls the connection of the first and second bit lines for executing the read/write test. Therefore, the erasable non-volatile semiconductor memory device according to the present invention can reduce the erasing process cycles, which requires a long time, falsely read out the '0' data and '1' data without writing actual data into each memory cell to shorten the test time, and thus can supply a low price product.