The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 1993
Filed:
Nov. 13, 1990
Paul D Ta, San Jose, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
A differential output buffer formed on a monolithic semiconductor substrate characterized by a bias generator coupled to a voltage source and a output stage coupled to the bias generator. The bias generator develops a bias output having a voltage level less than that of the voltage source. The output stage is responsive to a pair of complementary CMOS logic level inputs and uses the bias output of the bias generator to develop a pair of corresponding, low voltage swing outputs. In one embodiment the bias generator and the output stage operate in an open-loop and produce output signals which swing approximately two volts and in another embodiment the bias generator and the output stage operate in a closed-loop configuration and produce output signals which swing approximately one volt.