The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 1993

Filed:

Oct. 07, 1991
Applicant:
Inventors:

Laszlo J Dobos, Beaverton, OR (US);

Arthur J Metz, Gervais, OR (US);

Assignee:

Tektronix, Inc., Wilsonville, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
3241 / ; 3241 / ; 328151 ;
Abstract

A signal acquisition and sampling system mounted in an oscilloscope probe includes an input buffer amplifier (30) featuring shunt feedback, offset capability, input bias current compensation, and very low input capacitance. Signal sampling is accomplished by a cascaded pair of differential sampling bridges including a fast track-and-hold stage (40) followed by a slow track-and-hold stage (50). The differential configuration of the bridges features common mode rejection of strobe signal coupling into the signal path and reduces aberrations and voltage droop. The fast track-and-hold stage features Schottky diode switching bridges (42A) and (42B), low value storage capacitors (44A) and (44B), thereby resulting in a fast tracking time. The slow track-and-hold stage features low-leakage diode-connected transistor switching bridges (52A) and (52B) and a FET buffer stage, thereby resulting in fast acquisition of the fast stage output and long hold time for quantization of the sample. A strobe signal is coupled through a cable (72) to a timing generator (80) on integrated circuit (20). The strobe signal causes the fast track-and-hold stage to briefly hold samples of the input signal while simultaneously causing the timing generator to drive the slow track-and-hold stage to quickly acquire the output of the fast stage and hold the acquired value for extended time intervals. The bandwidth of the fast stage is thereby combined with the stability of the slow stage.


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