Bicmos ttl output buffer circuit with reduced power dissipation

Abstract

In a BiCMOS TTL output buffer circuit, bipolar output pullup and pulldown transistors (Q3,Q4,Q5) source and sink current at an output (V.sub.OUT). A phase splitter transistor (Q2,N4) is coupled to the bipolar output pullup and pulldown transistors for controlling respective conducting states in response to data signals at an input (V.sub.IN) during the active bistate mode of operation. CMOS tristate transistors (P1, ,P2,P4,N2) form a tristate circuit for implementing an inactive tristate mode at the output V.sub.OUT in response to tristate enable signals at a tristate enable input (OE). In order to reduce quiescent input current (I.sub.CC) power dissipation, an input power switch CMOS transistor (NI,N4,P1A) is coupled in the input current path to the high potential power rail (V.sub.CCI). The control gate node of the input power switch CMOS transistor (N1, ,N4,P1A) is coupled to the input (V.sub.IN) to control sourcing of input current (I.sub.CC) in response to data signals at the input during the active mode for reducing power dissipation. In the preferred example the input power switch CMOS transistor (N4) replaces and comprises the phase splitter transistor of the output buffer circuit. Dual CMOS phase splitter transistors (N4,N3) are also provided with the second dual CMOS phase splitter transistor (N3) coupled in an accelerating feedback circuit between the output (V.sub.OUT and the output pulldown transistor (Q5).