Logic circuit having sharper falling edge transition

Abstract

A logic circuit in which first and second transistors are connected in series between high and low potential power sources with the middle point of the series connection used as the output terminal; A same- and inverse-phase signal generating unit is provided connected between the high and low potential power sources in parallel with the first and second transistors for generating same- and inverse-phase signals based on the single input signal output from the logic circuit. A transient signal generating unit is provided for generating transient large current signals at the rise time of the inverse-phase signals and generating transient cut-off signals at the fall time of the inverse-phase signals. The series connected first transistor is driven and controlled based on the regular-phase signals, while the second transistor is driven and controlled based on the transient large current signal and transient cut-off signal, thus producing an inverse-phase output by a simple circuit construction.