The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 18, 1993
Filed:
Oct. 13, 1992
Shunsaku Ueda, Carlsbad, CA (US);
Kwai-Kwong Lam, Margarita, CA (US);
Craig Robertson, Mountain View, CA (US);
Silicon Systems, Inc., Tustin, CA (US);
Abstract
The present invention provides a linearized and delay compensated all CMOS voltage controlled oscillator. A transconductance converter receives a control voltage input and provides a control current to a current controlled ramping circuit that is responsible for providing two ramping voltage outputs to the positive inputs of two comparators. These comparators compare the ramping voltages to a threshold voltage and provide pulses to a latch when the ramping voltages cross the threshold voltage. The latch provides the oscillating output of the circuit which is fed back to the current controlled ramping circuit for switching purposes. A compensation loop receives both the oscillating output of the latch and the control current as inputs and provides the threshold voltage to the comparators. The compensation loop contains a similar current controlled ramping circuit which provides ramping outputs identical to those of the first current controlled ramping circuit. Track-and-hold circuits triggered by the oscillating outputs provide the peak voltages of the ramping outputs through a low-pass filter to the negative input of a difference amplifier. An external reference voltage is supplied to the positive input of the difference amplifier and the output of the difference amplifier is provided as the threshold voltage to the comparators. The effects of the comparator delay and the latch delay are cancelled out by the compensation loop.