The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 1993

Filed:

May. 28, 1986
Applicant:
Inventors:

Jeffrey P Kasold, San Jose, CA (US);

Chung H Lam, Troy, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B11C / ;
U.S. Cl.
CPC ...
365185 ; 36518909 ; 365218 ; 257320 ; 257325 ;
Abstract

A non-volatile memory cell uses two different areas for electron injection, allowing direct overwriting of previously stored data without an intervening erase cycle. A floating gate FET has dual programming gates disposed on its floating gate. Each programming gate includes a layer of dual electron injector structure (DEIS) and a polysilicon electrode. When writing a '0', one of the programming gates removes charge from the floating gate. When writing a '1', the other programming gate injects charge into the floating gate. The above charge transfer does not take place if the previously stored logic gate and the logic state to be written in are identical.


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