The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 1993

Filed:

Jul. 22, 1992
Applicant:
Inventors:

Toshio Hanazawa, Kasugai, JP;

Yukinori Fujimura, Owariasahi, JP;

Takashi Matsumoto, Inazawa, JP;

Assignees:

Fujitsu Limited, Kawasaki, JP;

Fujitsu VSLI Limited, Kasugai, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257378 ; 257566 ; 257577 ; 257587 ;
Abstract

A semiconductor device comprises a substrate of a first conduction type defined by a major surface, a pair of conductive regions of a second conduction type formed in the substrate along the major surface, an intervening region of the first conduction type formed in the substrate between the pair of conductive regions so as to separate the pair of conductive regions from each other, a first insulator film provided on the substrate so as to cover the major surface thereof including the pair of conductive regions and the intervening region located therebetween, a first conductor layer provided so as to extend generally parallel to the major surface of the substrate with a separation from the first insulator film, the first conductor layer crossing a part of the intervening region at a level separated therefrom, a second conductor layer provided on the first insulator film at a level below the first conductor layer so as to cover at least the part of the intervening region which is crossed by the first conductor layer, a second insulator film interposed between the second conductor layer and the first conductor layer, and a circuit for applying a predetermined voltage to the second conductor layer, the predetermined voltage having a magnitude chosen such that turning-on of a parasitic MOS transistor formed in the semiconductor device is eliminated.


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