The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 1993
Filed:
Feb. 26, 1990
John A Malleo-Roach, Lambertville, NJ (US);
Paul W Rutkowski, Morris Plains, NJ (US);
Eleanor Wu, Princeton, NJ (US);
AT&T Bell Laboratories, Murray Hill, NJ (US);
Abstract
Psuedo-exhaustive self-testing of an electronic circuit (10), containing groups of combinational elements (14.sub.1, 14.sub.2, 14.sub.3 . . . 14.sub.n), is accomplished by first partitioning the groups of combinational elements into sub-cones having no more than w imputs each by designating appropriate nodes ('test points') in each cone as the output of a sub-cone. A set of test vectors {a.sub.1, a.sub.2 . . . a.sub.w, b.sub.1, b.sub.2 . . . b.sub.w } is then generated (via an internal generator 74) such that when the vectors are applied to the sub-cones (14.sub.1.sbsb.a, 14.sub.1.sbsb.b . . . . 14.sub.i.sbsb.j), each sub-cone will be exhaustively tested. Each of the inputs of the sub-cones is assigned to receive a vector such that the vectors received at the inputs are linearly independent. The subset of vectors is applied through each of a plurality of pseudo-exhaustive self-test (PEST) flip-flop circuits (88) and through the test points to test the circuit. The PEST flip-flop circuits 88 also serve to advantageously compact and observe the response data produced by each sub-cone (14.sub.i.sbsb.j) with that of an upstream sub-cone.