Address generator for high speed data averager

Abstract

An address generator that provides equivalent time sampling for a time domain reflectometer generates read and write addesses for simultaneous application to an aquisition memory over an address bus. For each iteration of a repetitive input signal an excitation pulse is delayed by an amount, dt, that is an integer submultiple of a sampling period, T. Read addresses for each iteration of the repetitive input signal start from an initial address and increment by T/dt for each data sample. Corresponding write addresses are generated from the read addresses one sample time later so that the address on the address bus has a read address that is one address ahead of the write address. The acquisition memory reads out data from the read address for accumulation with corresponding sampled data while accumulated data is being input to the write address.