Process for forming extremely thin edge-connectable integrated circuit

Abstract

An edge connector is formed along a sidewall edge of a relatively thin semiconductor wafer. The wafer contains a signal processing circuit to which the edge connector is to be electrically joined. For this purpose a region of material capable of being bonded with conductive material is formed in the wafer and a trench pattern is formed in a first surface of the wafer, so as to expose a sidewall portion of the doped region. The doped region is connected to signal processing circuitry within the wafer. A metallic layer is then electroplated onto the exposed sidewall portion of the doped region. A layer of polishing resistant material, such as silicon nitride, is formed in the trench and the wafer is inverted and wax-mounted face down on a support member such that the first surface of the wafer faces the support member. The wafer is then polished as to effect a thinning of the wafer down to a level which exposes the polishing resistant material in the trench pattern. The polishing resistant material is then removed from the trench pattern, thereby leaving a plurality of spaced apart semiconductor dice that are supported by way of the support member. The dice are then removed from the support member by melting the wax. The thinned edge-connectable wafer may then be attached at its sidewall edges to conductive land portions of a separate substrate, such as one containing a focal plane array.