The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 1992

Filed:

Oct. 22, 1990
Applicant:
Inventor:

Tatsunori Murotani, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36523006 ; 36518909 ; 365205 ; 365233 ; 36518907 ;
Abstract

A semiconductor memory device comprises memory cell array, bit line pairs respectively coupled to the columns of the memory cells, sense amplifier circuits operative to increase small differences in voltage level on the bit line pairs, first and second voltage lines supplying a high voltage level and the ground voltage level through the sense amplifier circuits to the bit line pairs for increasing the small difference, and a driving circuit operative to activate the sense amplifier circuits, wherein the driving circuit comprises an equalizing circuit for equalizing the first and second voltage lines to an intermediate voltage level, a first transistor coupled between the first voltage line and a source of an external voltage level higher than the high voltage level, a second transistor providing a conduction path between a source of the second voltage level and the second voltage line in the presence of a control signal and isolating the second voltage line from the source of the second voltage level in the absence of the control signal, and a control circuit causing the first transistor to produce the high voltage level in the presence of another control signal and to isolate the first voltage line from the source of the external voltage level in the absence of the control signal.


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