The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 1992

Filed:

May. 30, 1989
Applicant:
Inventors:

Dennis D Everson, Banks, OR (US);

Philip R Lantz, Cornelius, OR (US);

Stanley R Koslowski, Tualatin, OR (US);

Assignee:

Tektronix, Inc., Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395700 ; 364D / ; 3642229 ; 364252 ; 3642592 ;
Abstract

A circuit for software performance analysis implements a balanced binary tree in hardware. This circuit consists of a number of 'levels', each containing two (sets of) latches, a RAM, and a digital comparator. One of the latches, the data latch, is used to hold the data element being evaluated. The other latch, the results latch, stores partial results based on the comparisons performed on higher levels. The RAM is addressed by the contents of the results latch on the preceding level in combination with the output of the comparator on that same preceding level. The output of the RAM is compared by the digital comparator with the contents of the data latch, to produce an additional bit of results information for the next level. On each level, the RAM is preprogrammed with twice as many midpoint addresses as is the RAM on the preceding level. The outcome of the comparison done on any particular level is used, along with the results from preceding levels, as an address to access a RAM on the next level. Eventually, the last level is reached and there is only one range for each address generated on that level. This address is then applied to a count-holding RAM, and the contents of that RAM at that location is incremented to indicate that the incoming data element was within this data range.


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