The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 1992
Filed:
Aug. 30, 1991
Michael J Allen, Rescue, CA (US);
Terry L Baucom, Folsom, CA (US);
Diana Esmail-Zandi, Cameron Park, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
The present invention discloses an improved two-stage macrocell for Programmable Logic Devices. According to the first stage of the improved circuit of the present invention's macrocell, combined NOR'ing, inverting, MUX'ing, and latching functions are performed by the single first stage. This single stage replaces the prior art multiple stages for performing the same NOR'ing, inverting, MUX'ing, and latching functions of the present invention. Since the present invention replaces the prior art multiple stages with a single stage, the speed of the present invention in performing the above NOR'ing, inverting, MUX'ing, and latching functions is significantly improved over the prior art. Furthermore, the present invention also discloses a second stage for a low-noise temperature-compensated output circuit. According to this aspect of the present invention, the low temperature noise on the ground and the supply voltage lines is reduced so that the low temperature noise approximately equals the high temperature noise on the ground and the supply voltage lines. Moreover, the speed improvement of the first stage of the present invention, described above, compensates for any speed degradation produced by the low-noise temperature-compensated output circuit of the second stage, so that the overall speed of the first and the second stages of the macrocell of the present invention is still improved over the prior art multiple-stage macrocell.