The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 1992
Filed:
Aug. 29, 1991
Koichiro Okumura, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A BiCMOS logic circuit, in one arrangement, includes an NPN bipolar transistor and a first NMOS connected in series. It also includes a CMOS logic circuit, an NMOS logic section, a PMOS and a second NMOS. The CMOS logic circuit conducts logical operation on input signals. The NPN bipolar transistor driven by a signal from the CMOS logic circuit has a base connected to the CMOS logic circuit, a collector connected to a power source and an emitter connected to an output terminal. The first NMOS has a drain connected to the output terminal and a source connected to ground. The NMOS logic section is connected between the power source and a gate of the first NMOS. The PMOS is connected in parallel with the NMOS logic section and receives at its gate the signal from the CMOS logic circuit, and the second NMOS is connected between the gate of the first NMOS and the ground and receives at its gate the signal from the CMOS logic circuit. In another similar arrangement, two NPN bipolar transistors are connected in series. The BiCMOS logic circuit thus arranged is capable of operating at a high speed under low power supply voltages.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile