Watchdog timer employing plural counters and discriminator for

Abstract

A watchdog timer capable of detecting clock signals when the opening frequency of a frequency source drifts lower or higher than a normal desired operating range, increasing circuit safety and reliability. The timer uses first and second clock oscillation circuits to generate first and second signals of frequencies f.sub.1 and f.sub.2 which are then divided by 1/N.sub.1 and 1/N.sub.2 in first and second frequency dividers, respectively. Third and fourth frequency dividers are used to divide the second frequency signal f.sub.2 by 1/N.sub.3 and 1/N.sub.4, respectively. A scale of N.sub.5 counter is connected to receive the f.sub.1 /N.sub.1 frequency signal as a clock input and the f.sub.2 /N.sub.3 frequency signal as a reset input, and provides an output signal at a frequency of (f.sub.1 /N.sub.1)/N.sub.5 which is less than f.sub.2 /N.sub.3 when the clock circuits are operating under normal conditions. A scale of N.sub.6 counter is connected to receive the f.sub.2 /N.sub.4 frequency signal as a clock input and the f.sub.1 /N.sub.2 frequency signal as a reset input, and provides an output signal at a frequency of (f.sub.2 /N.sub.4)/N.sub.6 which is less than f.sub.1 /N.sub.2 under normal conditions. A discrimination circuit is connected to monitor the outputs of the scale of N.sub.5 and N.sub.6 counters to determine the presence of a fault by detecting when either output no longer meets the associated relationship.