The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 1992
Filed:
May. 28, 1991
Applicant:
Inventor:
Takeo Tatematsu, Yokohama, JP;
Assignee:
Fujitsu Limited, Kanagawa, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 40 ; 357 45 ;
Abstract
A wafer scale integration device comprises a plurality of real chips formed in the center portion of a wafer and a plurality of dummy chips formed in the circumference of the wafer. The dummy chips only include relay pads, some of the relay pads are used for relaying bonding wires of power supply lines. Consequently, the power supply lines do not short-circuit at edge portions of the wafer, since a length of the bonding wire at the edge portion of the wafer becomes short due to the relay pad connected to the bonding wire.