The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 1992

Filed:

Oct. 24, 1990
Applicant:
Inventors:

Brian H Desilets, Wappingers Falls, NY (US);

Chang-Ming Hsieh, Fishkill, NY (US);

Louis L Hsu, Fishkill, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10L / ;
U.S. Cl.
CPC ...
437 32 ; 437 31 ; 437162 ; 357 34 ; 357 35 ;
Abstract

A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base region generally bounding a portion of the first region; forming by ion implantation a linking region of the second conductivity type in the surface of the bounded portion of the first region so as to electrically link generally opposing edges of the extrinsic base region through the linking region; forming an insulating spacer over the junction between the extrinsic base region and the linking region so as to generally bound a portion of the linking region within the portion of the first region; etching the surface of the bounded portion of the linking region a short distance into the linking region; forming by epitaxial growth a first layer of semiconductor material of the second conductivity type on the etched surface of the bounded portion of the linking region; heating the semiconductor substrate to form an intrinsic base region at least partially within the first layer and to form an electrical connection between the intrinsic and extrinsic base regions through the linking region; and forming a second region of the first conductivity type in the surface of the intrinsic base region.


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