Method for manufacturing capacitor of highly integrated semiconductor

Abstract

A method for manufacturing a capacitor of a highly integrated semiconductor memory device including a plurality of memory cells, each of which has a transistor and a capacitor. The method comprises the steps of forming an insulating layer for insulating the transistor, forming a contact hole to electrically connect to a source region by etching the insulating layer, sequentially forming a first polycrystalline silicon layer, an oxide layer, and a second polycrystalline silicon layer consisting of grains, exposing the second polycrystalline silicon layer to an oxide etchant, partially etching the oxide layer by the oxide etchant penetrating along the peripheries of the grains, anistropically etching the whole second polycrystalline silicon layer and, at the same time, the partial first polycrystalline silicon layer also, using the oxide layer being unaffected by the oxide etchant, as a mask, removing the oxide layer, forming a storage electrode by defining into cell units the first polycrystalline silicon layer, sequentially forming a dielectric film and a plate electrode formed of a third polycrystalline silicon layer over the resultant structure. Thus, the physical properties of the material itself is used without any specific conditions and unrestricted by limitation of minimum feature size. Furthermore, the process is greatly simplified and the effective capacitance of the cell capacitor is easily extended.