Method of manufacturing minimum counterdoping in twin well process

Abstract

An improved method for manufacturing high density CMOS integrated circuits which minimizes counterdoping of the N and P well structures includes providing a composite masking layer which has layers of silicon oxide, polycrystalline silicon and silicon nitride over a silicon monocrystalline substrate. A mask layer pattern is formed from the composite masking layer by lithography and anisotropic etching which removes the silicon nitride and the portion of the thickness of the polycrystalline silicon over areas designated to be the N well structure. The mask layer pattern is subjected to isotropic etching of the polycrystalline silicon to remove the remaining exposed thickness of polycrystalline silicon and to undercut etch the polycrystalline silicon under the silicon nitride portion of the mask layer pattern. The N well structure is ion implanted and formed by using the silicon nitride layer portion of the mask layer pattern as the mask. The silicon substrate over the N well and the exposed the polycrystalline silicon layer under the silicon nitride layer of the mask layer pattern is oxidized to form an N well silicon oxide pattern. The mask layer pattern is removed. The P well structure is ion implanted and formed using the N well silicon oxided pattern as the mask. The P well structure has minimized counterdoping by these process steps. All the silicon oxide from the surface of the silicon substrates are removed. Field oxide isolating structures are formed at the juncture of P well and N well structures.