The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 1992
Filed:
Nov. 05, 1990
Brent W Miller, Menlo Park, CA (US);
William W Walker, Los Gatos, CA (US);
Laurence H Cooke, San Jose, CA (US);
Vertex Semiconductor Corporation, Sunnyvale, CA (US);
Abstract
A scannable latch system comprises a plurality of scannable latches and clock driver circuit that allow at-speed testing of integrated circuits. Each scannable latch comprises a master latch, a slave latch and an auxiliary latch. The master latch is a two input latch capable of receiving data from two sources. The output of the master latch is coupled to the input of the slave and auxiliary latches. The clock driver circuitry receives a clock and control signals which are transformed into signals that operate the scannable latch in three different modes. In the normal mode, the slave latch is transparent and the data is held primarily in the master latch. In the scan mode, data may be shifted into the master, shifted out through the auxiliary latch, or shifted both in and out with a propagate function. Finally, in a test mode independent data values may be stored in the master latch and the slave latch.