The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 1992
Filed:
Sep. 09, 1991
Applicant:
Inventor:
Seiichi Iwamatsu, Suwa, JP;
Assignee:
Seiko Epson Corp., Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 68 ; 357 71 ; 437180 ;
Abstract
A method of forming thin film metal interconnects employed in integrated circuit structures comprising the step of laying out the interconnects so that the patterned interconnects have a relationship of interconnect width, L, and interconnect spatial separation, S, so that S>1 .mu.m>L. In particular, line width, L, is equal to or less than 0.8 .mu.m, spatial separation, S, is in the range of 1.0 .mu.m to 1.2 .mu.m and interconnect thickness, T.sub.A1, is about 0.5 .mu.m thereby providing effective optimization in the amount of reduction in interconnect spatial capacitance resulting in increased operation speed of the integrated circuit structure.