The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 1992

Filed:

Apr. 02, 1991
Applicant:
Inventors:

Lavi A Lev, San Jose, CA (US);

Ian A Young, Portland, OR (US);

Jeffrey K Greason, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307446 ; 307570 ;
Abstract

A BiCMOS logic circuit which implements single stage inverting and non-inverting logic functions is described. The circuit includes pull-up and pull-down assembly means coupled between the input and the non-inverting output nodes. The pull-down assembly means comprises a pair of complimentary metal-oxide semiconductor field-effect transistors connected in an inverter configuration in which the gates of the pair of CMOS transistors are coupled to the input node while the output of the inverter configuration provides the inverting output while driving the gate of a n-channel transistor coupled between the non-inverting output node and V.sub.ss.


Find Patent Forward Citations

Loading…