The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 1992
Filed:
Jul. 12, 1989
Tadashi Matsuno, Tokyo, JP;
Hideki Shibata, Yokohama, JP;
Kazuhiko Hashimoto, Tokyo, JP;
Hisayo Momose, Tokyo, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A method of manufacturing a semiconductor device having a semiconductor substrate of a first conductivity type, an N-type diffusion layer formed in the substrate, and a P-type diffusion layer formed in the substrate. Two contact holes are formed in separate steps, thus exposing the N-type diffusion layer and the P-type diffusion layer, respectively. Hence, when one of the diffusion layers is again doped with an impurity, or again heat-treated, the other diffusion layer is already protected by inter-layer insulation film. Therefore, the impurity cannot diffuse into the contact formed in the contact hole made in the other diffusion layer. As a result of this, SAC technique can be successfully achieved, without deteriorating the characteristic of the contact. In addition, since two contact holes are made in a polysilicon wiring strip and the diffusion layer to which the SAC technique is applied, in separate steps, the SAC technique can be successfully accomplished, without deteriorating the characteristic of the MOSFET formed in the semiconductor device.