The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 1992

Filed:

Jul. 25, 1991
Applicant:
Inventors:

Shoji Ariizumi, Tokyo, JP;

Fujio Masuoka, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 71 ; 357 234 ; 357 239 ; 357 59 ; 357 65 ;
Abstract

A semiconductor memory device including: a semiconductor substrate of a first conductivity type; triple-layer gate electrode structure formed on the semiconductor substrate and having first insulating film and second insulating film on upper and lower sides of the electrode; a pair of first impurity regions of a second conductivity type in the semiconductor substrate for contacting an opposite side face of the gate electrode structure; an impurity region selectively formed in a channel region corresponding to the data to be fixed in the memory device; an insulating wall on a portion of at least one side face of the gate electrode structure; a pair of second impurity regions of the second conductivity type in the substrate, each of the second regions overlapping with a corresponding one of the first impurity regions for contacting an opposite side face of the insulating wall; a contact pad layer connected to one of the second impurity regions for covering at least a portion of the first insulating film; and a wiring layer connected to the contact pad layer.


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